1. Field of the Invention
The present invention relates to a level shift circuit that generates an output signal for driving a high-side NMOS transistor included in a power semiconductor device.
2. Description of Related Art
A power semiconductor device such as a step-down DC-DC converter includes two switching elements connected in series between a power supply potential and a ground potential, and causes the two switching elements to complementarily turn on and off. To satisfy the need of miniaturization and long-term driving of an electronic device, an N-channel metal-oxide semiconductor (NMOS) transistor is used as a high-side (high-potential-side) switching element of the two switching elements. The NMOS transistor has a smaller mounting area than that of a P-channel metal-oxide semiconductor (PMOS) transistor, and has satisfactory characteristics such as an on-resistance characteristic. Therefore, the use of the NMOS transistor as the high-side switching element results in a reduction in mounting area of the switching element and an increase in efficiency.
The source potential of the high-side NMOS transistor changes from the ground potential (0 V) to about a power supply potential VCC (for example, 5 V). Accordingly, in order to drive the high-side NMOS transistor, a bootstrap circuit and a level shift circuit are required. The bootstrap circuit generates a high potential V_BOOT (for example, 2VCC=10 V) based on the power supply voltage, and supplies the high potential to drive buffers for directly driving each of the level shift circuit and the high-side NMOS transistor, and the like. Further, the level shift circuit converts the voltage amplitude of a pulse width modulation (PWM) control signal for on/off control of the high-side NMOS transistor. Specifically, the level shift circuit converts the PWM control signal whose level changes between the ground potential (0 V) and the power supply potential VCC (for example, 5 V), into an output signal whose level changes between the ground potential (0 V) and a maximum value of the high potential V_BOOT (for example, 10 V).
The level shift circuit includes a plurality of switching transistors. For this reason, attention should be paid to prevent a gate-source voltage and a drain-source voltage of the transistors provided in the level shift circuit from exceeding a predetermined breakdown voltage level. It is necessary for a level shift circuit in the prior art shown in FIG. 4 to use a high breakdown voltage transistor. On the other hand, a level shift circuit in the prior art shown in FIG. 5 can be formed using a transistor having a low breakdown voltage relative to a maximum potential difference between the high potential V_BOOT and the ground potential. The level shift circuits shown in FIGS. 4 and 5 are briefly described below.
A level shift circuit 50A shown in FIG. 4 is disclosed in Japanese Unexamined Patent Application Publication No. 11-205123. The level shift circuit 50A increases the voltage amplitude of the PWM control signal input to an input terminal 501 to thereby generate an output signal to be supplied to an output terminal 502. The source and back gate of each of NMOS transistors M1 and M2 are connected to the ground potential. The gate of the NMOS transistor M1 is supplied with the PWM control signal input to the input terminal 501. Meanwhile, the gate of the NMOS transistor M2 is supplied with an inverted signal of the PWM control signal, which is inverted by an inverter 503. Thus, when one of the transistors M1 and M2 turns on, the other of the transistors M1 and M2 turns off. In other words, the transistors M1 and M2 operate complementarily.
The source and back gate of each of PMOS transistors M3 and M4 are connected to a power supply potential VDD (for example, 10 V) which is boosted in order to drive the high-side NMOS transistor. The drain of the transistor M3 is connected to the gate of the transistor M4 and the drain of the transistor M4 is connected to the gate of the transistor M3 in a crossed manner. Also, the drain of the transistor M3 is connected to the gate of a PMOS transistor M5 for driving the high-side NMOS transistor, and to the drain of the NMOS transistor M1. Further, the drain of the transistor M4 is connected to the drain of the NMOS transistor M2.
When the power supply potential VDD supplied to the level shift circuit 50A shown in FIG. 4 is 10 V, a maximum value of each of a gate-source voltage VGS and a drain-source voltage VDS of the transistors M3 and M4 is about 10 V. Further, the maximum value of the drain-source voltage VDS of each of the transistors M1 and M2 is also about 10 V. Accordingly, the transistors M1 to M4 need to have a high breakdown voltage, that is, 10 V or higher. The use of the high breakdown voltage transistors causes an increase in chip area and an increase in the number of manufacturing steps, leading to an increase in manufacturing costs of the level shift circuit.
Meanwhile, a level shift circuit 50B shown in FIG. 5 which is a modified example of the level shift circuit 50A shown in FIG. 4 is disclosed in Japanese Unexamined Patent Application Publication No. 11-205123. The level shift circuit 50B includes four clamp transistors M51 to M54. The PMOS transistor M51 and the NMOS transistor M53 are connected in series between the drain of the transistor M3 and the drain of the transistor M1. Further, the PMOS transistor M52 and the NMOS transistor M54 are connected in series between the drain of the transistor M3 and the drain of the transistor M1. The gates of the transistors M51 to M54 are connected to the power supply potential VDD through a Zener diode 504, and are biased by a constant bias voltage V_BIAS (for example, VDD/2).
In the level shift circuit 50B shown in FIG. 5, the drain potential of each of the transistors M1 and M2 is clamped to the bias voltage V_BIAS (V_BIAS−threshold voltage Vth, to be exact) or lower through the operations of the four clamp transistors M51 to M54. Further, the drain potential of each of the transistors M3 and M4 is clamped to the V_BIAS (V_BIAS+threshold voltage Vth, to be exact) or higher. In other words, appropriate setting of the V_BIAS enables the level shift circuit 50B to suppress an excessive rise of the gate-source voltage VGS and drain-source voltage VDS of each of the transistors M1 to M4. Consequently, the level shift circuit 50B can be produced using a transistor having a low breakdown voltage relative to the maximum potential difference between the power supply potential VDD and the ground potential.